Implementación de funciones de tranferencia en VHDL

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-- A | B | f0 | f1
-- ---------------
-- 0 | 0 | 0  | 0
-- 0 | 1 | 1  | 0  
-- 1 | 0 | 1  | 1
-- 1 | 1 | 1  | 1    
--


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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Problema1 is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           F0 : out  STD_LOGIC;
           F1 : out  STD_LOGIC);
end Problema1;

architecture Funcional of Problema1 is
begin
process(A,B)
begin
if(A='0' and B='0')then
F0<='0';
else
F0<='1';
end if;
if(A='0') then
F1<='0' ;
else
F1<='1';
end if;
end process;
end Funcional;

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# PlanAhead Generated physical constraints

NET "A" LOC = U10;
NET "B" LOC = V8;
NET "F0" LOC = T19;
NET "F1" LOC = R20;