Contador 0 - 15 VHDL (solo simulacion)

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Problema3 is
    Port ( Q : BUFFER  STD_LOGIC_vector(3 DOWNTO 0):="0000";
       CLOCK : IN  STD_LOGIC
 );
end Problema3;

architecture Contador of Problema3 is
BEGIN
counter:   PROCESS (Q, CLOCK)
BEGIN
IF (CLOCK'EVENT AND CLOCK ='1')THEN
Q<=Q+1;

   END IF;
   END PROCESS;
end Contador;