Contador 20 BITS en VHDL

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-- CONTADOR
--  contador ascendente/descendente de n bits…
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Contador is
    Port ( CLOCK : in  STD_LOGIC;
           CLC_E : in  STD_LOGIC;
           A, R : in  STD_LOGIC;
           S : buffer  STD_LOGIC_VECTOR(20 DOWNTO 0));
end Contador;

architecture COUNT of Contador is
signal temporal: std_logic;
signal contador: integer range 0 to 49999999:=0;
signal Salida: std_logic;
begin
divisor_frecuencia: process(R, clock)
begin
if(R='1') then
temporal<='0';
contador<=0;
elsif (rising_edge(clock)) then
if(contador=49999999) then
temporal<= not(temporal);
contador<=0;
else
contador<=contador+1;
end if;
end if;
end process;
Salida<=temporal;

counter: process (R, Salida)
begin
if (R ='1') then
S<="000000000000000000000";
elsif (Salida'EVENT and Salida ='1' and CLC_E ='0')then
if (A='1') then
S<=S+1;
else
S<=S-1;
      end if;
   end if;
end process;
end COUNT;

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NET "R" LOC = "T15" | IOSTANDARD = LVCMOS33 | PULLDOWN;

NET "CLOCK" LOC = E12;

NET "A" LOC = T9;

NET "CLC_E" LOC = V8;

NET "S[20]" LOC = AA6;

NET "S[19]" LOC = AA4

NET "S[18]" LOC = AB3

NET "S[17]" LOC = AA3

NET "S[16]" LOC = AB2;

NET "S[15]" LOC = Y18;  

NET "S[14]" LOC = W18;  

NET "S[13]" LOC = V17;   

NET "S[12]" LOC = W17;  

NET "S[11]" LOC = AA21;  

NET "S[10]" LOC = AB21;

NET "S[9]" LOC = AA19;   

NET "S[8]" LOC = AB19;  

NET "S[7]" LOC = R20;  

NET "S[6]" LOC = T19;  

NET "S[5]" LOC = U20;  

NET "S[4]" LOC = U19; 

NET "S[3]" LOC = V19; 

NET "S[2]" LOC = V20; 

NET "S[1]" LOC = Y22;

NET "S[0]" LOC = W21;