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sábado, 6 de junio de 2015

Sumador de 5 bits

Programa principal

----------------------------------------------------------------------------------
-- Practica 3
-- Implementar la instanciación en VHDL de un sumador completo de n
-- bits, donde n está en el rango de [0:5] bits. 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.suma.all;
entity SUMADORF is
 port( A,B : in  std_logic_vector(5 downto 0):="000000";
   CIN : in  std_logic:='0';
SALIDA   : out std_logic_vector(5 downto 0);
CARRY: inout std_logic;
n : in  std_logic_vector(2 downto 0):="001");
end SUMADORF;

architecture SUMATORIA of SUMADORF is
signal C : std_logic_vector(5 downto 0):="000000";
begin
process(A,B,CIN,n)
begin 
case n is
when "001" =>
C(0)<=CIN;
SALIDA(0)<=SUMA(A(0),B(0),C(0));
CARRY<=COUT(A(0),B(0),C(0));
when "010" =>
C(0)<=CIN;
SALIDA(0)<=SUMA(A(0),B(0),C(0));
C(1)<=COUT(A(0),B(0),C(0));
SALIDA(1)<=SUMA(A(1),B(1),C(1));
CARRY<=COUT(A(1),B(1),C(1));
when "011" =>
C(0)<=CIN;
SALIDA(0)<=SUMA(A(0),B(0),C(0));
C(1)<=COUT(A(0),B(0),C(0));
SALIDA(1)<=SUMA(A(1),B(1),C(1));
C(2)<=COUT(A(1),B(1),C(1));
SALIDA(2)<=SUMA(A(2),B(2),C(2));
CARRY<=COUT(A(2),B(2),C(2));
when "100" =>
C(0)<=CIN;
SALIDA(0)<=SUMA(A(0),B(0),C(0));
C(1)<=COUT(A(0),B(0),C(0));
SALIDA(1)<=SUMA(A(1),B(1),C(1));
C(2)<=COUT(A(1),B(1),C(1));
SALIDA(2)<=SUMA(A(2),B(2),C(2));
C(3)<=COUT(A(2),B(2),C(2));
SALIDA(3)<=SUMA(A(3),B(3),C(3));
CARRY<=COUT(A(3),B(3),C(3));
when "101" =>
C(0)<=CIN;
SALIDA(0)<=SUMA(A(0),B(0),C(0));
C(1)<=COUT(A(0),B(0),C(0));
SALIDA(1)<=SUMA(A(1),B(1),C(1));
C(2)<=COUT(A(1),B(1),C(1));
SALIDA(2)<=SUMA(A(2),B(2),C(2));
C(3)<=COUT(A(2),B(2),C(2));
SALIDA(3)<=SUMA(A(3),B(3),C(3));
C(4)<=COUT(A(3),B(3),C(3));
SALIDA(4)<=SUMA(A(4),B(4),C(4));
CARRY<=COUT(A(4),B(4),C(4));
when "110" =>
C(0)<=CIN;
SALIDA(0)<=SUMA(A(0),B(0),C(0));
C(1)<=COUT(A(0),B(0),C(0));
SALIDA(1)<=SUMA(A(1),B(1),C(1));
C(2)<=COUT(A(1),B(1),C(1));
SALIDA(2)<=SUMA(A(2),B(2),C(2));
C(3)<=COUT(A(2),B(2),C(2));
SALIDA(3)<=SUMA(A(3),B(3),C(3));
C(4)<=COUT(A(3),B(3),C(3));
SALIDA(4)<=SUMA(A(4),B(4),C(4));
C(5)<=COUT(A(4),B(4),C(4));
SALIDA(5)<=SUMA(A(5),B(5),C(5));
CARRY<=COUT(A(5),B(5),C(5));
WHEN OTHERS =>
C(0)<='0';
SALIDA<=(OTHERS=>'0');
CARRY<='0';
END CASE;
END PROCESS;
END SUMATORIA;

-----------------------------------------------------------------------------------------------------------------------


Paquete 1


library IEEE;
use IEEE.STD_LOGIC_1164.all;

package paquete1 is

function xorm2 (signal ent1 : in std_logic;
signal ent2 : in std_logic)
return std_logic;

function xorm3 (signal ent1 : in std_logic;
signal ent2 : in std_logic;
signal ent3 : in std_logic)
return std_logic;
end paquete1;

package body paquete1 is

--------------------------------------------
--compuerta XOR2
function xorm2 (signal ent1 : in std_logic;
signal ent2 : in std_logic)
return std_logic is
variable sal2: std_logic;
begin
if (ent1 /= ent2) then 
  return '1';
else
return '0';
end if;
return sal2;
end xorm2; 
-------------------------------------------
--compuerta XOR3
function xorm3 (signal ent1 : in std_logic;
signal ent2 : in std_logic;
signal ent3 : in std_logic)
return std_logic is
variable sal3: std_logic;
begin
if(ent1='0' and ent2='0' and ent3='1')then
return '1';
   elsif(ent1='0' and ent2='1' and ent3='0')then
return '1';
   elsif(ent1='1' and ent2='0' and ent3='0')then
return'1';
   elsif(ent1='1' and ent2='1' and ent3='1')then
return'1';
   else 
return'0';
  end if;
  return sal3;
  end xorm3;

end paquete1;
--------------------------------------------------------------------------------------------------------------------


Funciones de Suma y Carry


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.paquete1.all;

package suma is
--  funciones de suma y de Cout; acarreo

 function suma   (signal a  : in std_logic;
  signal b  : in std_logic;
signal Cin: in std_logic) return std_logic;
 function Cout  (signal a  : in std_logic;
signal b  : in std_logic;
signal Cin: in std_logic) return std_logic;
end suma;

package body suma is
--Funcion de suma para la suma de un bit.
 function suma  (signal a  : in std_logic;
 signal b  : in std_logic;
 signal Cin: in std_logic) return std_logic is
      variable qwe: std_logic; 
   begin
      qwe:= xorm3(a,b,Cin); 
      return qwe; 
    end suma;
----------------------------------------------------------------
--Funcion de bit de acarreo.
function Cout  (signal a  : in std_logic; 
signal b  : in std_logic;
   signal Cin: in std_logic) return std_logic is
variable qwer: std_logic;
begin
qwer:=(a and b) or (cin and(xorm2(a,b)));
return qwer;
end Cout;
end suma;


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