Simulacion de Memorias en VHDL

RAM Sincrona de 1 Puerto

----------------------------------------------------------------------------------
-- Practica 8
-- Memoria RAM sincrona de puerto sencillo
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

entity RAM_SINC_1P is
GENERIC( AD : INTEGER:=12;
         DA : INTEGER:=8 );
Port ( CLK, W : in  STD_LOGIC;
ADR : IN STD_LOGIC_VECTOR(AD-1 DOWNTO 0);
DIN : IN STD_LOGIC_VECTOR(DA-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(DA-1 DOWNTO 0) );
END RAM_SINC_1P;

ARCHITECTURE DATOS of RAM_SINC_1P IS
TYPE RAMDAT IS ARRAY(2**AD-1 DOWNTO 0)
OF STD_LOGIC_VECTOR(DA-1 DOWNTO 0);
SIGNAL RAM : RAMDAT;
SIGNAL ADRRES : STD_LOGIC_VECTOR(AD-1 DOWNTO 0);
BEGIN

PROCESS(CLK)
BEGIN
IF(CLK' EVENT AND CLK='1') THEN
IF(W='1') THEN
RAM(TO_INTEGER(UNSIGNED (ADR))) <= DIN;
END IF;
ADRRES <= ADR;
END IF;
END PROCESS;
DOUT <= RAM(TO_INTEGER (UNSIGNED (ADRRES)));
END DATOS;

RAM Sincrona de doble Puerto

----------------------------------------------------------------------------------
-- Practica 8
-- Memoria RAM sincrona de puerto doble
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

entity RAM_SINC_2P is
GENERIC( AD : INTEGER:=6;
         DA : INTEGER:=8 );
Port ( CLK, W : in  STD_LOGIC;
ADR_A : IN STD_LOGIC_VECTOR(AD-1 DOWNTO 0);
ADR_B : IN STD_LOGIC_VECTOR(AD-1 DOWNTO 0);
DIN : IN STD_LOGIC_VECTOR(DA-1 DOWNTO 0);
DOUT_A : OUT STD_LOGIC_VECTOR(DA-1 DOWNTO 0);
DOUT_B : OUT STD_LOGIC_VECTOR(DA-1 DOWNTO 0));
END RAM_SINC_2P;

ARCHITECTURE FUNC of RAM_SINC_2P IS
TYPE RAMDAT IS ARRAY(0 TO 2**AD-1)
OF STD_LOGIC_VECTOR(DA-1 DOWNTO 0);
SIGNAL RAM : RAMDAT;
SIGNAL ADRRES_A, ADRRES_B : STD_LOGIC_VECTOR(AD-1 DOWNTO 0);
BEGIN

PROCESS(CLK)
BEGIN
IF(CLK' EVENT AND CLK='1') THEN
IF(W='1') THEN
RAM(TO_INTEGER(UNSIGNED (ADR_A))) <= DIN;
END IF;
ADRRES_A <= ADR_A;
ADRRES_B <= ADR_B;
END IF;
END PROCESS;
DOUT_A <= RAM(TO_INTEGER (UNSIGNED (ADRRES_A)));
DOUT_B <= RAM(TO_INTEGER (UNSIGNED (ADRRES_B)));
END FUNC;

RAM Asincrona de 1 Puerto

----------------------------------------------------------------------------------
-- Practica 8
-- Memoria RAM asincrona de puerto sencillo
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

entity RAM_ASINC_1P is
GENERIC( AD : INTEGER:=8;
         DA : INTEGER:=1 );
Port ( CLK, W : in  STD_LOGIC;
ADR : IN STD_LOGIC_VECTOR(AD-1 DOWNTO 0);
DIN : IN STD_LOGIC_VECTOR(DA-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(DA-1 DOWNTO 0) );
END RAM_ASINC_1P;

ARCHITECTURE DATOS of RAM_ASINC_1P IS
TYPE RAMDAT IS ARRAY(2**AD-1 DOWNTO 0)
OF STD_LOGIC_VECTOR(DA-1 DOWNTO 0);
SIGNAL RAM : RAMDAT;
BEGIN

PROCESS(CLK)
BEGIN
IF(CLK' EVENT AND CLK='1') THEN
IF(W='1') THEN
RAM(TO_INTEGER(UNSIGNED (ADR))) <= DIN;
END IF;
END IF;
END PROCESS;
DOUT <= RAM(TO_INTEGER (UNSIGNED (ADR)));
END DATOS;

RAM Asincrona de doble Puerto

----------------------------------------------------------------------------------
-- Practica 8
-- Memoria RAM asincrona de puerto doble
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

entity RAM_ASINC_2P is
GENERIC( AD : INTEGER:=6;
         DA : INTEGER:=8 );
Port ( CLK, W : in  STD_LOGIC;
ADR_A : IN STD_LOGIC_VECTOR(AD-1 DOWNTO 0);
ADR_B : IN STD_LOGIC_VECTOR(AD-1 DOWNTO 0);
DIN : IN STD_LOGIC_VECTOR(DA-1 DOWNTO 0);
DOUT_A : OUT STD_LOGIC_VECTOR(DA-1 DOWNTO 0);
DOUT_B : OUT STD_LOGIC_VECTOR(DA-1 DOWNTO 0));
END RAM_ASINC_2P;

ARCHITECTURE DATOS of RAM_ASINC_2P IS
TYPE RAMDAT IS ARRAY(0 TO 2**AD-1)
OF STD_LOGIC_VECTOR(DA-1 DOWNTO 0);
SIGNAL RAM : RAMDAT;
BEGIN

PROCESS(CLK)
BEGIN
IF(CLK' EVENT AND CLK='1') THEN
IF(W='1') THEN
RAM(TO_INTEGER(UNSIGNED (ADR_A))) <= DIN;
END IF;
END IF;
END PROCESS;
DOUT_A <= RAM(TO_INTEGER (UNSIGNED (ADR_A)));
DOUT_B <= RAM(TO_INTEGER (UNSIGNED (ADR_B)));
END DATOS;

ROM Sincrona

----------------------------------------------------------------------------------
-- Practica 8
-- Memoria ROM sincrona
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity xilinx_rom_sync_template is
port (
clk : in std_logic;
addr : in std_logic_vector(3 downto 0);
data: out std_logic_vector (6 downto 0)
);
end xilinx_rom_sync_template;

architecture arch of xilinx_rom_sync_template is
constant ADDR_WIDTH: integer := 4 ;
constant DATA_WIDTH: integer := 7 ;
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0 );
constant HEX2LED_ROM: rom_type:= ( -- 2 * 4 - by - 7
"0000001", -- addr 00
"1001111", -- addr 01
"0010010", -- addr 02
"0000110", -- addr 03
"1001100", -- addr 04
"0100100", -- addr 05
"0100000", -- addr 06
"0001111", -- addr 07
"0000000", -- addr 08
"0000100", -- addr 09
"0001000", -- addr 10
"1100000", -- addr 11
"0110001", -- addr 12
"1000010", -- addr 13
"0110000", -- addr 14
"0111000"  -- addr 15
) ;

signal addr_reg : std_logic_vector (ADDR_WIDTH-1 downto 0 );
begin
-- addr register to infer block RAM
process (clk)
begin
if (clk'event and clk = '1') then
addr_reg <= addr;
end if;
end process;
data <= HEX2LED_ROM (to_integer (unsigned (addr_reg))) ;
end arch;

ROM Asincrona

----------------------------------------------------------------------------------

-- Practica 8

-- Memoria ROM Asincrona 

----------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity rom_template is

port(

addr: in std_logic_vector (3 downto 0);

data: out std_logic_vector (6 downto 0)

);

end rom_template;

architecture arch of rom_template is

constant ADDR_WIDTH: integer :=4;

constant DATA_WIDTH: integer := 7;

type rom_type is array (0 to 2**ADDR_WIDTH-1)

of std_logic_vector (DATA_WIDTH-1 downto 0 );

--ROM definition

constant HEX2LED_ROM: rom_type :=(--2^4-by-7

"0000001", -- addr 00

"1001111", -- addr 01

"0010010", -- addr 02

"0000110", -- addr 03

"1001100", -- addr 04

"0100100", -- addr 05

"0100000", -- addr 06

"0001111", -- addr 07

"0000000", -- addr 08

"0000100", -- addr 09

"0001000", -- addr 10

"1100000", -- addr 11

"0110001", -- addr 12

"1000010", -- addr 13

"0110000", -- addr 14

"0111000"  -- addr 15

);

begin

data <= HEX2LED_ROM(to_integer(unsigned(addr)));

end arch;